Interpolator for machine tool control

ABSTRACT

A machine tool control has an interpolator, including a feed rate generator and a function generator, for providing first and second trains of command pulses for controlling movement of machine tool slides along mutually perpendicular axes in respective dependence upon the first and second command pulses. The feed rate generator and the function generator employ pulse rate multipliers for modifying the pulse rate of a basic pulse train to provide the first and second command pulses. A normalizing process is employed to reduce the amount of electronics required as well as to reduce the clock rates within the interpolator. Each rate multiplier serves to multiply a received pulse rate by a fraction. Normalization is achieved by effectively varying the value of the numerator of this fraction in the feed rate generator rate multiplier and the denominator of the fraction in the function generator rate multipliers. An improved pulse rate multiplier, referred to herein as an adder rate multiplier, is disclosed and is particularly applicable for use in the function generator.

United States Patent Sindelar Feb. 4, 1975 INTERPOLATOR FOR MACHINE TOOL Primary Examiner-Malcolm A. Morrison CONTROL Assistant ExaminerJerry Smith 75 l t E t F. I l nven or 0215281 Smde ar, Moreland H1lls, [57] ABSTRACT A machine tool control has an interpolator, including [73] Ass'gneei The warn" Swasey Company, a feed rate generator and a function generator, for Clevelandi Ohm providing first and second trains of command pulses 22 Fil d; Aug. 29 1973 for controlling movement of machine tool slides along mutually perpendicular axes in respective dependence [21] Appl' 392,684 upon the first and second command pulses. The feed rate generator and the function generator employ 52 us. (:1 1. 235/151.11, 235/152, 318/571, Pulse rate multipliers for modifying the pulse rate of 3 3 573 basic pulse train to provide the first and second com- 511 Int. Cl. 006i 15/46 "land P A normalizing Process is p y to tss] Field of Search 235115031, 15111, 152; duce the amount of electronics required as well as w 313/570 57 573 reduce the clock rates within the interpolator. Each rate multiplier serves to multiply a received pulse rate 5 Ref Cited by a fraction. Normalization is achieved by effectively UNITED STATES PATENTS varying the value of the numerator of this fraction in 3 the feed rate generator rate multiplier and the denomg f inator of the fraction in the function generator rate 372S654 W973 gg 235/151 multipliers. An improved pulse rate multiplier, re- 313si104 5/1973 Holmg r e n zr.12:13:: 3l8/57l x ferred herei as an adder mullipllei is closed and is particularly applicable for use in the function generator.

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PATENTEI] FEB 41975 SHEET 8 OF 9 NMM 1 INTERPOLA'TOR FOR MACHINE TOOL CONTROL This invention relates to the art of machine tool control and more particularly to improvements in providing command pulses for use in controlling movement of 5 a machine tool.

The present invention is particularly applicable for use in providing command pulses for controlling slide movement along two axes to obtain movement ofa cutting tool relative to a workpiece with the two axes being mutually perpendicular and referred to hereinafter as axes X and Z. The invention may be employed in other applications, such as for controlling movement ofa machine tool along three mutually perpendicular axes.

It has been known in the art to utilize an interpolator for providing command pulses for controlling movement of a machine tool in accordance with slide motion along mutually perpendicular X and Z axes. The interpolator includes a feed rate generator and a function generator. The feed rate generator provides feed rate pulses having a pulse rate in dependence upon the value of a feed rate number FRN. This feed rate number represents the ratio of a desired vectorial velocity F to the vectorial summation of programmed departure distances along the X and Z axes. For a two axis control, this vectorial summation may be considered as the hypotenuse H, wherein H is the square root of the sum of the squares of the programmed departure distances along the X and Z axes. The feed rate pulses are supplied to the function generator which generates two pulse trains to provide command pulses for movement ofa tool slide along the X axis and command pulses for controlling movement of a tool slide along the Z axis. Such a function generator employs two rate multipliers for respectively modifying the pulse rate of the feed rate pulses in accordance with a programmed departure distance for the Z axis and the programmed departure distance for the X axis. The function generator may provide these pulses to achieve linear or circular modes of operation.

It is known in such machine tool control, that the electronics required may be decreased to effectively increase the operation speed of the system by normalizing the programmed information or calculated information utilized to develop multiplying signals for the pulse rate multipliers. Typically, normalization has been achieved by effectively varying the numerator in the multiplying fraction used in multiplying the received pulses. This type of normalization technique is employed in both the feed rate generator and in the function generator. The normalization process typically requires that each signal to be normalized be introduced as a binary number and placed in a shift register. Then the binary numbers are shifted until the most significant bit of the largest binary number is positioned in the most significant bit position of its shift register.

It is an object of the present invention to provide a machine tool control having a different normalization process than that of the prior art wherein the normalization process effectively changes the value of the denominator in the multiplying fraction used in the rate multipliers employed in at least one of the generators in the interpolator.

It is a still further object of the present invention to achieve normalization wherein the numerator in the multiplying fraction is varied for the feed rate generator multiplier while the denominator in the multiplying fraction is varied for the function generator multipliers.

it is a still further object of the present invention to provide an improved interpolator for a machine tool control wherein the process of normalization in the function generator includes varying the value ofthe denominator of the multiplying fraction of each of the two rate multipliers employed in accordance with the value of the larger of two received input signals representing programmed departure distances along the mutually perpendicular axes.

It is a still further object of the present invention to provide a control for a machine tool wherein the interpolator employs an improved rate multiplier which includes an adder and an accumulator and wherein an input modifying signal applied to the adder is added in parallel with the contents of the accumulator and the summation is applied to the accumulator at a rate corresponding with the pulse rate of pulses applied to the accumulator.

in accordance with one aspect of the present invention, the control includes a feed rate generator and a function generator. The feed rate generator receives pulses derived from a pulse source at a first pulse rate and includes a first pulse rate multiplier for modifying the pulse rate of the received pulses in accordance with a multiplier fraction having a value M/N to provide a train of feed rate pulses. The value of the denominator N is fixed and corresponds with the maximum number of states of the multiplier and the value of M is a variable first modifying pulse having a value in dependence upon the normalized values of first, second, and third signals which respectively represent programmed departure distances along the first and second axes and the programmed vectorial velocity. The function generator includes second and third pulse rate multiplying means for receiving the feed rate pulses and multiplying the pulse rate thereof by a multiplying signal M'/N, where M for the second rate multiplier has a value corresponding with that of the first signal and M for the second rate multiplier has a value corresponding with the second signal. For these rate multipliers, however, the denominator N is variable and has a maximum value of the same amount for each of the second and third rate multipliers corresponding with the maximum number of states of these rate multipliers. Normalization of the first and second signals is effectively achieved by varying the value of the denominator N by the same extent for each of the second and third multipliers in dependence upon the value of the larger of the first and second signals.

In accordance with another aspect of the present invention, the control includes a feed rate generator as well as a function generator. The feed rate generator includes at least a first rate multiplier for modifying the pulse rate of received pulses in dependence upon the value of a first modifying signal to provide feed rate pulses. The function generator includes second and third pulse rate multipliers for modifying the pulse rate of the feed rate pulses in dependence upon the value of a second modifying signal and a third modifying signal to provide first command pulses and second command pulses for controlling movement of the tool. In this aspect of the invention, at least one of these rate multipliers includes an accumulator and an adder. The adder is initially loaded to a value corresponding with that of an associated one of the modifying signals and supplies a summation output in parallel to update the accumulator contents. The contents of the accumulator are applied in parallel to the adder for parallel addition. This operation takes place at a rate corresponding with the received pulses. Carry output pulses are derived from the adder in such a manner that the output pulses have a pulse rate in dependence upon the value of the applied modifying signal and that of the received pulses.

DESCRIPTION OF THE DRAWINGS The foregoing and other objects and advantages of the invention will become more readily apparent from the following description of the preferred embodiments of the invention as taken in conjunction with the accompanying drawings which are a part hereof and wherein:

FIG. I is a block diagram illustration of one application of the present invention to a machine tool control system;

FIG. 2 is a schematic-block diagram illustration of the interpolator control circuitry constructed in accordance with the present invention;

FIG. 3 is a simplified block diagram of the hypotenuse calculator;

FIG. 4 is a graphical illustration used in explaining the operation of the hypotenuse calculator;

FIG. 5 is a schematic-block diagram illustration of the hypotenuse calculator;

FIG. 6 is a schematic-block diagram illustration of the ratio calculator;

FIG. 7 is a flow diagram illustration of the operation of the ratio calculator;

FIG. 8 is a block diagram illustration of an adder rate multiplier circuit employed in the function generator;

FIG. 9 presents graphical illustrations of wave forms used in illustrating the operation of the adder rate multiplier of FIG. 8;

FIG. 10 is a schematic-block diagram illustration of the circuitry employed in the function generator;

FIG. I1 is a schematic-block diagram illustration of the arc gating control circuitry employed in the function generator;

FIG. 12 is a graphical illustration showing quadrants of a circle used in describing the operation of the function generator; and,

FIG. 13 is a graphical illustration showing an arc of a circle and which is used in describing the circular interpolation operation of the function generator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS General Description Reference is now made to the drawings wherein the showings are for purposes of illustrating preferred embodiments of the invention only and not for purposes of limiting same. FIG. 1 is a block diagram illustrating a machine tool control system embodying the present invention for purposes of controlling movement of a machine tool along mutually perpendicular axes X and Z. This is known as a two axis machine tool control system. One application for such a control system is in conjunction with controlling a two axis turning machine. Whereas the invention is described with respect to such a two axis machine. it is to be appreciated that the various features may be employed in other applications, such as for controlling a three axis machine.

It is contemplated that the machine to be controlled includes a cross slide 10 having a longitudinal slide 12 mounted thereon for respective movement along X and Z mutually perpendicular axes. As is conventional. these slides are driven simultaneously in response to pulses from a pulse source so that a cutting tool is moved along a path corresponding with the vectorial summation ofmovements of the slides l0 and 12 along the X and Z axes. This may be achieved by employing each slide in a digital control loop. As illustrated in FIG. I, the X axis slide 10 is located in a digital control loop XL which includes a servo motor SM-l. This servo motor is drivingly connected to a lead screw 14, threaded to slide 10, for driving the slide at a velocity dependent upon the value of a digital error signal provided by a bidirectional counter BC-I. This digital error signal represents a pulse count and is converted into an analog representation thereof by means of a conventional digital-to-analog converter D-l. The magnitude of the analog signal controls the energization of the servo motor and hence, the angular velocity, neglecting load conditions. This causes a corresponding angular velocity of lead screw 14. The movement of slide 10 is at a linear velocity dependent upon the angular velocity of the lead screw and its pitch length.

A rotary pulse generator PG-l may be connected to the lead screw 14, so as to be driven thereby, for purposes of providing a pulse train having a fixed number of output pulses for each revolution of the lead screw. Whereas the pulse generator PG-l is illustrated herein as being a rotary pulse generator, other pulse generators may be employed, such as the linear feedback laser interferometer disclosed in the U.S. patent to Ralph l-I. Schuman 3,648,276 assigned to the same assignee as the present invention.

The pulse generator PG-l preferably includes two tracks in quadrature so as to provide two trains of feedback pulses which are applied to a digitizer Dll. The digitizer Dl-l serves to combine the two pulse trains and determine therefrom the direction of angular rotation of the lead screw. The digitizer provides an output feedback pulse train having a fixed number of pulses per revolution of the lead screw and these feedback pulses are applied to one input of an anticoincidence circuit AC-l. Command pulses F are also applied to the anticoincidence circuit and these are obtained from a function generator FG, to be discussed in greater detail hereinafter. These command pulses exhibit a pulse rate which dictates the velocity of slide 10. The command pulses F and the feedback pulses from digitizer Dl-l are applied by the anticoincidence circuit AC-l to the up/down bidirectional counter BC-l. The anticoincidence circuit AC-l serves to prevent either a command pulse or a feedback pulse from being lost in the event that the two pulses occur simultaneously or overlap.

The up/down bidirectional counter BC-l serves as an accumulating register to produce a digital position error signal. This is a function of the number of pulses applied to the up input and the number of pulses applied to the down input of the counter. The bidirectional counter provides a digital position error signal which is converted into an analog signal by the digitalto-analog converter D-1 and is then amplified by amplifier A-l and supplied to control the servo motor 8M4. The slide 10 is then driven at a linear velocity along the X axis in dependence upon the magnitude of the error signal.

The digital control loop ZL for controlling movement of slide 12 along the Z axis by a lead screw 16, is structured and operates in the same manner as that discussed hereinabove with respect to the X axis control loop XL. Consequently, similar components in the two loops are identified with similar reference characters to simplify the description of the invention herein. The command pulses F for the Z axis control loop are obtained from the function generator PG and the pulse rate dictates the linear velocity of slide 12 along the Z axis.

Each feedback pulse represents a basic incremental distance, such as 0.0001 inches. Similarly, each com mand pulse represents a basic incremental desired distance of movement, such as 0.0001 inches. For linear operation then, if the programmed departure distance for the X axis is representative of 3 inches, the X axis servo control loop XL will receive exactly thirty thousand command pulses from an X displacement control circuit XDC. As will be discussed hereinafter, this control circuit may take the form of a down counter which receives a displacement command for the programmed X departure distance and then meters the appropriate number of command pulses F to the X axis control loop. A similar Z displacement control circuit ZDC meters command pulses F, to the Z axis control loop.

lnterpolator Circuitry With reference to FIG. 1, the interpolator generally includes a feed rate generator FRG and a function generator FG. This is a pulse rate control system in that each command pulse F; or F commands a specific length of travel of a tool. For example, each command pulse may represent a commanded displacement of 0.0001 inch along an associated axis. The pulse rate of the command pulses commands a certain axis velocity. For example, one KHz pulse rate may represent a rate of 6 inches per minute. Although, in the preferred embodiment, the information is coded in binary format, it is to be appreciated that the circuitry employed may be used with binary coded decimal or straight decimal coded information.

The interpolator control circuit functions to reduce a high frequency input clock signal by programmed inputs to an output pulse rate proportional to the programmed inputs and to distribute these pulses to the X axis control loop XL and the Z axis control loop ZL to generate a programmed path. The high frequency input signal originates from one of two sources. The source depends upon whether the programmed operation is to be in terms of tool velocity as a function of time or tool velocity as a function of spindle speed. If the programmed operation is to be dependent on spindle speed in inches per revolution, then this will normally be referred to herein as an [PR operation mode. in the lPR mode, the basic pulse rate F applied to the feed rate generator FRG will be obtained from a suitable spindle generator SG. On the other hand, if the programmed operation requires that tool velocity be a function of time, then this will normally be referred to hereinafter as an [FM operation mode. In the [PM mode, the basic pulse rate F will be based on clock pulses obtained from a high frequency clock source CS.

The interpolator control circuitry reduces the basic pulse rate F to a lower pulse rate in accordance with programmed inputs obtained from a data distribution and control circuit BBC and then distributes the command pulses F and F to the X control loop XL and the Z axis control loop ZL.

The data distribution and control circuit DDC receives instructions from a conventional tape reader TR and then distributes commands to the interpolator control circuitry. The program itself may be recorded upon a suitable tape such as a multitrack, punched paper tape T which is read by a conventional tape reader TR. It is contemplated that the program will include blocks of information for various cutting operations. Each block may include a programmed desired vectorial velocity F which may be expressed in terms of inches per revolution lPR or in terms of inches per minute lPM. [f the program requires [PR operation, then control circuit DDC actuates a suitable circuit, represented by a single pole, double throw switch 20 to connect the output of the spindle generator SG to the feed rate generator FRG so that the basic pulse rate F is dependent upon spindle speed. 0n the other hand, if the operation commanded is lPM, then switch 20 is actuated to connect the clock source CS with the feed rate generator FRG so that the basic pulse F is dependent upon that of the clock source.

Each block of information also includes X and 2 words which provide command information dictating the commanded displacement of the slides along the X and Z axes, respectively. This is the normal incremental programming for use in linear interpolation. However, for circular interpolation, the X word is referred to as the l word and the Z word is referred to as the K word. For circular interpolation, the incremental distance from the center of the arc to be traced to the beginning of the arc as measured along the X and Z axes is programmed as the l and K words respectively. The arc center is the point about which the radius of the arc is rotated. Consequently then, the l word defines the ad dress for the arc center offset as measured along the X axis and the K word represents the address for the arc center offset as measured along the Z axis.

In addition, each block includes a G word which serves as a preparatory command coded to call for such functional operations as linear interpolation, circular interpolation in a clockwise direction, and circular interpolation in counterclockwise direction. The G word along with an X sign and a 2 sign are applied to the function generator PG for use in controlling circular interpolator operation. The structure and operation of the feed rate generator and function generator will be described hereinafter in greater detail.

lnterpolator Control (FIG. 2)

Referring now to FIG. 2, the interpolator control circuit is illustrated in greater detail than that shown in H6. 1. More specifically, the feed rate generator FRG includes a feed rate override control circuit FC which serves to receive pulses at the basic rate F 0 and reduce the pulse rate in manually selectable 10 percent steps from 0 percent to percent of the programmed rate. The output pulse rate is referred to as F This pulse train is then further reduced by a scaling circuit SC which serves to reduce the pulse rate by a factor for purposes of compensating for normalization techniques employed at a later point. The pulse rate of pulses obtained from the scaling circuit SC is referred to as pulse rate F Pulse rate R; is further reduced by a ratio rate multiplier RMF in dependence upon a modifier obtained from a ratio calculating circuit RC. The purpose of normalization and circuitry involved will be discussed in greater detail hereinafter. The ratio is the normalized vectorial velocity number/F/ to the normalized hypotenuse number The hypotenuse is the vectorial summation of the programmed X and Z displacements and is equal to the square root of the sum of the squares of the programmed departure distances. In linear interpolation, the X displacement word is treated as the I word and the Z displacement is treated as the K word. The hypotenuse calculator circuit HC receives the l word and the K word and then develops an output signal which is equal to the normalized hypotenuse H/ which is a function of the actual hypotenuse H. The ratio calculator RC receives the F word and the normalized hypotenuse word H/. The F word is normalized in the ratio calculator scaling circuit so that the output signal from the ratio calculator is proportional to the ratio of the normalized /F/ word to the normalized hypotenuse word This ratio is employed as a modifier by the rate multiplier RMF to reduce the pulse rate F to a pulse rate F Pulse rate F serves as the cutter velocity pulse rate and is fed to the function generator PG.

The function generator F6, to be described in detail hereinafter, serves to receive pulses at the cutter velocity pulse rate Fey and distribute command pulses F and F to the X control loop XL and the 2 control loop 2L. The function generator FG includes an I counter IC and a K counter KC which provide modifiers to an I rate multiplier IRM and to a K rate multiplier KRM. The l counter lC serves in linear interpolation as a means for storing the X word and similarly, the K counter serves in a linear interpolation for storing the 2 word. In circular interpolation these counters operate as counters for generating an arc in accordance with the programmed arc center offset l word and K word. The l (or X) word is normalized so that the F pulse rate is proportional to the product of a constant, the pulse rate P and the normalized /l/ word. Similarly, the K (or Z) word is normalized and used as a modifier for the K rate multiplier KRM such that the output pulse rate F; is proportional to the constant, the cutter velocity pulse rate F and the normalized /K/ word.

The output pulse rate F or F; is an unnormalized pulse rate. This follows since, as will be appreciated from the discussion of normalization hereinafter, that the output of the scaling circuit SC is a pulse rate R, which, when multiplied by the ratio /F///H/, provides an output pulse rate F which is proportional to the ratio of the unnormalized F word and the normalized hypotenuse When this pulse rate is multiplied by the normalized /l/ word at the rate multiplier IRM, the output pulse rate F is proportional to the programmed vectorial velocity F and the ratio of the normalized l/ word to the normalized /H/ word. The ratio of the normalized /l/ word to the normalized /H/ word is equal to the ratio of the unnormalized l word to the unnormalized H word and consequently, the output pulse rate F; is the unnormalized pulse rate. The same is true for pulse rate F For linear interpolation, the X displacement control XDC and the Z displacement control ZDC respectively receive an X word and a Z word. These controls may take the form of presettable down counters which are preset in accordance with the programmed displacement distances represented by the X word and the Z word. These circuits serve to meter the appropriate number of pulses at the pulse rate F or F to the respectively associated digital control loops XL and ZL. ln circular interpolation the l and K words represent the incremental distance from the center of the arc to the beginning of the arc, as measured along the X and Z axes. The are center is the point about which the radius of the arc is located. The function generator is provided with a G word (see FIG. I) which serves to command either clockwise or counterclockwise and the 1 counter serves as a counter and the K counter serves as a counter rather than storage registers, as in the linear mode of operation. The output from the K rate multiplier KRM is supplied as an input to the l counter and similarly the output of the I rate multiplier lRM is supplied as an input to the K counter. This circuitry serves to effectively trace an arc and its mode of operation and circuitry will be described in detail hereinafter.

Having provided a general description of the circuitry and mode of operation of the interpolator cir cuitry, attention is now directed to the following description which deals in greater detail with the specific circuitry employed and the operation involved.

Normalization All of the data provided to the interpolator control circuitry is processed in the natural binary form in the embodiment of the invention illustrated herein. The F, l and K words may be obtained from the tape reader in BCD format. If so, it is contemplated that the words be converted to a natural binary form for use by the sealing circuitry in scaling the basic pulse rate F to a lower pulse rate. These words are also normalized. This is done by shifting the binary numbers in registers such that the results fall within a fixed range of values. This is done for two reasons; namely, to reduce the amount of electronics. required and yet maintain the required velocity accuracy, and to reduce the clock rates within the interpolator control. The normalized values are compensated for in the feed rate generator FRG and in the function generator FG.

In the feed rate generator FRG, the inputs i.e., the X, Z, I, and K words are normalized such that the larger number is between I and 2. In terms of IPM operation then, the calculated hypotenuse will be normalized between 1 and 2.828 inches. The hypotenuse is calculated each time displacement information is read into the interpolator control. The F word is also normalized with the use of a register such that it is shifted to a normalized value between 1 and 2. The ratio of the normalized word to the normalized hypotenuse word /H/ is calculated with the use of the ratio calculating circuit RC.

The interpolator data is processed in natural binary form. This may be accomplished, for example, by multiplying each X and Y commanded displacement by a factor 10 in order to convert any real numbers to natural decimal numbers. The result is then converted into a natural binary number and normalized (converted to a real binary number) in the hypotenuse calculator. For example, if the programmed real number for the X axis displacement is 3.0, the natural decimal number would be 30,000. Similarly, if the programmed Z axis real number is 4.0 inches, the natural decimal number would be 40,000. When a natural decimal number of 30,000 is converted into a natural binary number, the binary number is lll0l0l00l 10000. This natural binary number when converted into a normalized (real) binary number is 0.11101010011.The rational decimal equivalent of this normalized binary number is the function 30,000/32,768 for a real decimal equivalent (approximately of 0.916). If a natural decimal number of 40,000 be converted into a natural binary number, the number would be 1001110001000000. The normalized real binary number would be 1.001110001. The rational decimal equivalent then is the fraction 40,000/32,768 for a real decimal equivalent (approximately) of 1.221. The hypotenuse calculation for this triangle then is 1.526 inches (real decimal equivalent of the normalized binary hypotenuse).

The programmed F word in [PM is multiplied by 10 to convert it a natural decimal number. This is then converted into a natural binary number and the natural binary number is normalized to produce a real binary number between 1 and 2. Table 1 below illustrated the conversion of an F word of 10.0 in 1PM.

The output of the ratio calculator then is the ratio of 1.563 to 1.526 or 1.024. The pulse rate is reduced in 1PM by a still further factor of 4 so that the output frequency rate F F (l.024)/(4).

1n the function generator FG, the input pulse rate F is divided into two output pulse rates F and F ln the preferred form of the invention, the function generator does not employ counter rate multipliers for pulse rate modification. Instead, the function generator employs arithmetic circuits, to be described in detail hereinafter, to modify the pulse rates. Also, unlike the feed rate generator FRG, which normalizes by shifting the numbers the function generator preferably employs circuitry normalization by adjusting the denominator of the transfer equation. Adjusting the denominator effectively adjusts the size of the function generator to the displacements or radius programmed. The function generator employs adder-accumulator registers for modifying input pulse rates. Carry signals from selected bits of the function generator adders are used as output pulses. By selection of the proper carry bit used for the function generator output, the size (denominator of the transfer equation) is adjusted. The selection of the carry bit is determined by the size (most significant bit) of the larger of the two modifier inputs (1 word and K word).

In the normalizing operation in the feed rage generator FRG, the decimal F word is always treated as a full four digit number without a decimal point. The F word is normalized by dividing it by an even binary multiple equal to or 'ust less than the F number so that the normalized F word is less than 2 and equal to or greater than 1. The denominator (next even binary multiple) is referred as to 2". For example if the F word, when converted to a natural decimal number, is 1,230, then the even binary multiple which is equal to or just less than the F number would be 1,024. This is equal to 2" where m equals 10. The normalized /F/ word then would be the ratio 1,230/1,024, which is equal to 1201171875, if carried out to 10 decimal places. 1n order to determine the denormalized F word, the normalized /F/ word must be multiplied by 2'"; that is, F (/F/ 2'". The scaling control circuit sc, as will be described hereinafter, multiplies the pulse train by 2". When this factor 2" is multiplied with the ratio /F///H/, the output pulse rate F is proportional to the ratio of the unnormalized F word to the normalized hypotenuse word H When this pulse rate multiplied by the normalized l word in the function generator FG, the output pulse rate F is proportional to the ratio of the normalized l word to the normalized H word multiplied by the unnormalized F word. Consequently then, this is essentially the same thing as stating that the output pulse rate F is proportional to the ratio of the unnormalized l word to the unnormalized H word multiplied by the unnormalized F word.

In the following sections, detailed descriptions are presented with respect to the circuitry employed in the feed rate generator and the function generator. These descriptions will further discuss the manner in which the circuitry achieves normalization.

Feed Rate Override Circuit Provisions are made for manual adjustment to achieve feed rate override in selectable 10 percent steps from 0 percent to 120 percent of the programmed rate. This is accomplished with the feed rate override circuit FC illustrated in FIG. 2. A feed rate override number PRO is supplied to a feed rate multiplier FRM for purposes of reducing the basic pulse rate F in selectable 10 percent steps of the programmed rate. The output frequency from the rate multiplier is referred to as frequency rate F The feed rate multiplier FRM may take any conventional form such as a 12 bit binary rate multiplier which basically is comprised of a binary up counter, called a multiplier counter, that counts the input pulses and gating circuitry, called multiplier gates, that gate the counter with a modifier input and the input pulses to produce an output frequency. All of the rate multipliers employed in the feed rate generator FRG may take this form. The modifier for the feed rate multiplier FRM is the feed rate override number FRO X (indicative of 100 percent) and divided by a factor of 2. Consequently then, the total modifier applied to the multiplying input of the rate multiplier is (FRO) 100/2.

The feed rate override rate multiplier FRM may be a six bit multiplier and in such case, the binary pattern of the FRO word is a six bit binary pattern. The binary pattern is representative of the percentage override desired in 10 percent steps. The pattern may be selected by an operator manipulating a switch to supply a selected binary number for a selected FRO word. This may be implemented in the manner as shown in P16. 1 wherein a switch arm 21 is illustrated as being selectively engageable with one of a plurality of circuits each of which provides a binary FRO word for application to the feed rate multiplier FRM. It is to be appreciated that such FRO words would include modification so that the FRO word is in effect multiplied by 100 and divided by a factor of 2. Consequently then, with a six bit feed rate override rate multiplier, the output frequency F is proportional to F (FRO)/(2") 100.

Feed Rate Scaling Circuit The feed rate scaling circuit SC provides compensation for the F word normalization which takes place in the feed rate generator. As will be recalled from the discussion dealing with normalization, the normalized F word may be denormalized by multiplying it by 2'" which is equal to the next lower even binary multiple to the binary F word. This follows because the normalized F word is equal to the binary F word divided by 2". This scaling circuit is illustrated in FIG. 2 to which attention is now directed.

The scaling circuit SC includes a twelve bit scaling rate multiplier SRM for receiving a modifying number 2". This rate multiplier is a I2 bit rate multiplier and has a numeric base of 2. Consequently then, the scaling rate multiplier serves to multiply pulse rate F by the ratio of 2" to 2' or F (TU/(2).

The factor 2" is found by using only the most significant bit of the binary F word. This is accomplished in the embodiment of the invention illustrated herein by applying the binary F word as a 12 bit word to a l2 bit, parallel to serial shift register FR-I. This shift register receives the F word as a parallel input and upon receipt of shift input pulses provides a bit serial output with the most significant bit being shifted first and the least significant bit being shifted last. In shifting this binary number from the F register RF-I, the most significant bit 2" is detected as the bits are shifted into a serial to parallel shift register FR-Z. This operation is commenced upon closure of a suitable load actuating switch represented herein by a normally open switch 30. Closing switch 30 causes a binary I signal to enable an AND gate 32. This permits AND gate 32 to pass clock pulses from a suitable clock source CK. Clock source CK may be associated with clock source CS or may be a separate source of clock pulses. These clock pulses from source CK are used as shift pulses for shifting the F word from register FR-I into register FR-Z. It is only necessary that the 12 bits of the F word be shifted and consequently, only 12 clock pulses need to be provided. This may be accomplished with the use of a presettable pulse counter 34 which serves to enable an AND gate 36 for a count of N, where N corresponds to 12 pulses. This permits AND gate 36 to pass twelve pulses. Thereafter, the N counter 34 disables AND gate 36. The output pulses from AND gate 36 are applied to a clock or shift input of register FR-Z so that a bit serial pulse train may be entered into this twelve bit register. The clock pulses are also applied to the shift input of register FR-l so the bit pattern stored in register FR-l is shifted one bit at a time with the most significant bit being shifted first. The output from the register FR-l is applied through a normally enabled AND gate 38 to register FR-2.

As the bit pattern from register FR-l is being shifted into register FR-Z, a flip-flop 40 operates to detect the location of the most significant bit of the F word. This is accomplished by connecting the output of the least significant bit stage of register FR-Z to the reset input of flip-flop 40. Consequently then, when the first significant bit of the F word is shifted into register FR-Z, the flip-flop 40 will be reset to disable AND gate 38. The AND gate then will carry a binary level signal at its output and this signal is applied to the input of register F R-2. Thereafter, each clock pulse applied to the clock input of register FR-Z, will shift a binary 0 level signal into the register. Only one bit position of register FR-Z will have a logic one level signal when the shift operation is completed. The twelve bit output pattern from register FR-Z provides a modifier binary number of 2" and this is used in scaling the pulse rate F with the scaling rate multiplier SRM.

Hypotenuse Calculator The hypotenuse calculator serves to calculate the hypotenuse of the right triangle formed by the X and Z displacements in linear interpolation or the l and K arc center offsets in circular interpolation. In the preferred embodiment of the invention, to be described in detail with reference to FIG. 5, the inputs to the hypotenuse calculator are normalized so that the larger number is between I and 2. However, before dealing with the specific circuitry employed in FIG. 5, reference is made to FIGS. 3 and 4 which respectively present a simplified block diagram illustration of the hypotenuse calculator together with a graphical illustration of the operation.

The hypotenuse calculator includes a presettable down counter IDC which is initially set to count condition in accordance with the number represented by the programmed I word. The calculator also includes a presettable up counter KUC which is initially set to a count condition corresponding with the K word. As will be discussed hereinafter, these counters are preferably multistage binary counters, although for the purposes of this discussion, they may be considered as decimal counters. The down counter IDC has its output applied to a pulse rate multiplier RM-l for purposes of multiplying an input frequency signal F by the count in the down counter to obtain an output pulse rate F Similarly, the up counter has its output applied to an associated rate multiplier RM-2 for purposes of multiplying the input frequency rate F by a modifier in dependence upon the count in the up counter to obtain an output frequency rate F The output frequency F from the up counter rate multiplier RM-2 is applied to the count input of the presettable down counter whereas the output frequency F from the down rate multiplier RM-l is applied as an input to the up counter KUC. During operation, the input frequency pulses F are applied to both rate multipliers RM-I and RM-Z. The up counter KUC counts in an upward direction for each pulse in accordance with the pulse rate F The down counter counts down one increment for each pulse applied thereto at a pulse rate F A zero detect circuit ZD serves to monitor the output of the down counter IDC and operates to stop clock pulses F from being applied to the rate multipliers when the count condition of the down counter has reached a zero count status. At this point, the count status of the up counter KUC is a count representative of the value of the hypotenuse H. That is, once the zero detect circuit has detected a zero count condition of the down counter IDC, the count status of the up counter KUC is a value equal to the square root of the sum of the squares of the initial counts preset into the down counter and the up counter.

This operation may be more readily understood from an examination of the graphical illustration of FIG. 4. If the initial count for the X axis be represented by X and that for the Z axis be represented by 2 then a right triangle having a hypotenuse H is defined. The vector representation of H describes a point X Z on an arc of the circle having a radius signal to B. As the down counter counts down and the up counter counts up, the point defined by the end of the vector traces an arc of a circle. When the down counter has reached a zero count, the value of X is zero. At this point, the hypotenuse H is equal to the final value of the Z count in the up counter.

Detailed Description of Hypotenuse Calculator Circuitry In the preceding discussions, the hypotenuse calculator BC was discussed with reference to a simplified showing and did not include normalization of the infor' mation data. Preferably, the invention is practiced by employing a hypotenuse calculator which includes normalization and a preferred embodiment of the calculator is illustrated in FIG. 5. For purposes of simplifying an understanding of the invention, the comparable circuits in FIGS. 3 and 5 are labeled with like character references.

The l word and the K word obtained from the tape reader by means of the data distribution and control circuit may be stored in parallel to serial storage registers 50 and 52 of FIG. 5. The number of bit stages employed is dependent upon the accuracy of resolution required in the operation. For example, each storage register may take the form of a bit storage register. The l word and the K word stored in registers 50 and 52 are stored as natural binary numbers. Each of these registers is operative as a shift register to shift the stored binary number in bit serial sequence with the most significant bit being shifted first and the least significant bit being shifted last in synchronism with shift pulses applied to the respective shift inputs of the registers. These shift inputs are clock pulses obtained from a clock source CKH. This clock source may be incorporated in a master clock that includes the clock source CS or the clock CK described herein with reference to FIG. 2. The pulse rate of the shift pulses from the clock source CKH may be relatively high, such as on the order of 5.6 ml-lz. The shift pulses from clock source CKH are applied to the shift inputs of registers 50 and 52 through an AND gate 54 when this gate has been enabled by a flip-flop 56. This flip-flop is normaliy in its reset condition to maintain AND gate 54 disabled. However, when AND gate 54 is enabled to supply shift pulses to registers 50 and 52, the contents of these registers are shifted in bit serial fashion and loaded into serial to parallel shift registers 60 and 62 respectively. During this process as will be discussed below, the l word and the K word are normalized.

The loading of shift registers 60 and 62 is commenced by providing a suitable load signal represented herein by closure of a normally open switch 64. This actuates a suitable one shot circuit 66 which applies a binary 1 pulse to the clear input of each of the registers 60 and 62. This is conventional in the art and serves to effectively reset the registers so that all bit positions are occupied by binary 0 level signals. This binary 1 pulse from the one shot circuit 66 is inverted by an inverter 68 which applies a momentary binary 0 pulse to the C input of flip-flop 56. This pulse has a negative going transition which is then followed by a positive going transition. The positive edge serves to actuate the flipflop. This flip-flop may take various forms. Preferably, it takes the form known as a combined RS and D flipflop. This type of flip-flop has a D input and a C input. The flip-flop also has a Q output and a 0 output. In addition, the flip-flop is provided with a set input 8 and the reset input R. As is known, if a binary 1 level signal is applied to the D input, then upon application of a positive going pulse to the C input, the flip-flop will be actuated to a state wherein the 0 output terminal carries a binary 1 signal and the 0 terminal carries a binary 0 signal. Consequently then, the one shot circuit provides a positive pulse for purposes of clearing the shift registers and 62 and the trailing edge of that pulse is used by flip-flop 56 to provide a binary l signal to enable AND gate 54. There is a slight time delay before AND gate 54 is enabled and this time delay is sufficient to permit the shift register 60 and 62 to be cleared.

With AND gate 54 being enabled by flip-flop 56, the shift clock pulses from clock source CKH are applied to the shift inputs of storage registers 50 and 52 as well as to the shift inputs of the l shift register 60 and the K shift register 62. The data in registers 50 and 52 is then simultaneously shifted in bit serial sequence into registers 60 and 62 respectively.

Normalization of the l word data and the K word data is achieved by an operation which includes detecting the most significant bit of the larger of the two words. This is achieved by connecting an OR gate to receive the binary level signal of the most significant bit position of each register 60 and 62. Consequently then, when the most significant bit of the larger of the two words is shifted into the most significant bit position of its associated register 60 or 62, this condition is detected by OR gate 70 which applies a binary l signal to the reset input R of flip-flop 56. This causes the output of flip-flop 56 to change state so that the 0 output terminal carries a binary 0 signal to disable AND gate 54 and thereby prevent further shift pulses from clock source CKH from being applied to registers 50, 52. 60 and 62.

While shifting the data from registers 50 and 52 into registers 60 and 62, the data is also loaded into the 1 down counter [DCand the K up counter KUC. That is, shift register 60 is a serial input to parallel output shift register for loading the l down counter. The K shift register 62 is also a serial input to parallel output shift register for loading the K up counter KUC. When the most significant bit of the larger of the two words I and K has been detected, flip-flop 56 is reset. This causes a one shot circuit '72 to apply a load triggering pulse to the load inputs of the l down counter [DC and the K up counter KUC so that the normalized I word is loaded into the l down counter and the normalized K word is loaded into the K up counter. These counters are now preset to count conditions corresponding with the normalized I count and the normalized K count. Preferably, the 1 counter and the K counter have the same number. of bit positions as the shift register and the K shift register respectively. In the example being given, each counter is a 12 bit binary counter. The l2 bit binary pattern representing the count status of each counter is applied to an associated rate multiplier for purposes of reducing an input pulse rate to a lower pulse rate. In the case of the 1 down counter lDC, its output is applied to a l2 bit binary rate multiplier RM-l whereas the output of the K up counter is applied to an associated binary rate multiplier RM-Z. The output pulse rate from the rate multiplier RM-l is applied as input count pulses to the count input of the K up counter where the output pulse rate of rate multipiier RM-2 is applied as count pulses to the count input of the down counter.

The calculating operation is commenced after the l counter and the K counter have been loaded. One shot circuit 72 applies a positive pulse to cause this loading operation. This output pulse is inverted by an inverter 74 so that a momentary binary pulse is applied to the C input of a flip-flop 76. Since flip-flop S6 is in its reset condition, it applies a binary 1 signal to the D input of flip-flop 76. Consequently then, on the trailing or positive going edge of the binary 0 signal pulse from inverter '74, flipflop 76 is actuated. This causes a binary 1 signal to be applied by its O output to enable an AND gate 78. This AND gate then passes clock pulses from the clock source CKH which serve as the input frequency rate F,-,, to the rate multipliers RM-l and RM2.

The down counter IDC will now count down in accordance with the pulse rate of the pulses obtained from the up counter rate multiplier RM2 while the up counter KUC counts in an up direction in accordance with the pulse rate of the pulses provided by the down rate multiplier RM-l. As discussed hereinbefore with reference to the showing in FIG. 3, when the down counter has obtained a count condition of zero, the count provided by the up counter KUC is of a value corresponding with the normalized hypotenuse H This condition is detected with zero detector ZD connected to the output of the down counter lDC. Once a zero count condition has been detected, the zero detec' tor ZD applies a trigger pulse to reset flip-flop 76 and thereby disable AND gate 78 to prevent further pulses from being applied to the rate multipliers RM-l and RM2. The output of the up counter KUC is a 12 bit binary signal and is of a value corresponding with the normalized hypotenuse H .This signal is now used by the ratio calculator RC for purposes of calculating the ratio ofthe normalized F word to the normalized H word.

Ratio Calculator The ratio calculator RC (FIG. 2) calculates the ratio of the normalized F word to the normalized hypotenuse word H The circuitry employed to perform this calculation preferably takes the form as that as illustrated in FIG. 6 to which attention is now directed.

The F word is stored in natural binary form in a parallel input to serial output storage register 80. The input supplied to the register may be supplied from the data distribution and control circuit DDC in accordance with information read by the tape reader TR. Register 80 may be a conventional 12 bit parallel input to serial output shift register which serves to provide an output in bit serial fashion as clock pulses are applied to the shift input of the register. The output pattern presents the most significant bit first and the least significant bit last. The F word stored in register 80 is shifted in bit serial sequence into an accumulator shift register 82 when the shift load input S/L receives a binary 1 signal. This accumulator shift register is conventional in the art and may receive a binary signal for storage with the signal being received in bit serial fashion or with the signal being received in bit parallel fashion. The mode of operation depends upon whether a binary l signal or a binary 0 signal is applied to the shift-load input S/L. When a binary 1 signal is applied to this input, one bit of information is shifted into the shift register in series fashion for each clock pulse applied to the clock input of the shift register. When a binary 0 signal is applied to this shift-load 8/1., a multiple bit binary signal is shifted in parallel for storage when a clock pulse is applied to the clock input CLK.

The operation of the ratio calculator may commence once the accumulator shift register 82 has been loaded with the F word and the hypotenuse calculator has completed its calculation. Information in the F shift register may be shifted into register 82 on command from various sources. In the embodiment illustrated, the tape reader TR serves to decode an end of block EOB designation by means of a decoder 84 and in response thereto, sets a flip-flop 86. This flip-flop then provides a load A signal which indicates that the accumulator shift register is to be loaded. The accumulator register will hereinafter be frequently referred as to the A register. The load A signal is applied as a binary l signal to the shift-load input S/L of the accumulator register 82 to condition the register to receive the F word in bit serial fashion. The load A signal also enables AND gates 88 and 89. This permits clock pulses from a suitable clock source CKR to be passed by AND gate 89 to register 80 and by AND gate 88, through an OR gate 90 to register 82. Clock source CKR may be a portion of a master clock which also includes clock sources CS (FIG. 1) or CK (HO. 2) or CKH (FIG. 5). As the clock pulses are applied to registers 80 and 82, the F word is shifted in bit serial fashion from register 80 into register 82. The F word is normalized when shifted into register 82 by detecting when the most significant bit of the F word is located at a particular bit position of the 12 bit accumulator register 82. The selected bit position for this 12 bit register is bit position 10. Consequently, when this bit position is occupied by a binary I level signal, an output taken from this position of the accumulator register serves to reset flip-flop 86. This removes the load A signal to prevent further shift pulses from being applied to register 80. In this manner, the F word from register 80 has been loaded into register 82 and normalized.

The calculating operation of the ratio calculator commences when a flip-flop is set. This may be accomplished in various ways. In the embodiment illustrated herein, when flip-flop 86 is in its set condition, its O output provides a load A signal. This is a binary l signal and is inverted by an inverter 102 to disable an AND gate 104 and thereby prevent flipflop 100 from being set. Once the accumulator has been loaded, flipflop 86 is reset and its output terminal 0 provides a binary 0 signal. This is inverted by inverter 102 to enable AND gate 104. This condition is indicative that the F word has been loaded in accumulator register 82. The ratio calculation also requires that the normalized hypotenuse word H has been calculated (FIG. 5). Consequently, during the time that the hypotenuse calculator is performing its calculating operation, it is desirable that flip-flop 100 not be in its set condition to cause a ratio calculation. This may be accomplished by employing a switch which serves to disable AND gate 104 so long as the hypotenuse is being calculated. in the embodiment illustrated, this is illustrated by a simple normally open switch 106 which is actuated to a closed condition during the hypotenuse calculation op eration to apply a binary l signal which is then inverted by an inverter [08 to disable AND gate 104. Once, however, the accumulator register 82 has been loaded and the hypotenuse calculation has been completed, both inputs to AND gate 104 are satisfied and flip-flop 100 is actuated to its set condition. When this flip-flop is in its set condition, its output terminal 0 carries a binary 1 signal indicative of a command for ratio calculate. This binary 1 signal is applied by flip-flop 100 to enable an AND gate 110 to pass clock pulses from clock source CKR to the clock input CLK of accumulator shift register 82. Since flip-flop 86 is reset, a binary signal is applied to the shift-load input S/L of register 82. Consequently then, in the absence of other instructions, each clock pulse will cause a parallel loading of information into the register of the binary information from the sum output of a full adder 112 to be discussed hereinbelow.

When flip-flop 100 is set, it also enables an AND gate 114 to pass clock pulses from the clock source CKR through the AND gate and thence, through a succeeding OR gate 116 to the clock input of a ratio shift register 118. This register is constructed somewhat similar to that of the accumulator register 82 in that it includes provisions for receiving information shifted therein in series or in parallel. Thus, register 118 has a shift-load input S/L. When the signal level applied to this input is at a binary 1 level, the ratio register 118 will be loaded in parallel for each clock pulse applied by OR gate I16 to the clock input. The ratio register 118 is initially preset to place a binary 1 level signal in its least significant bit position. This may be implemented by permanently connecting the parallel input for the least significant bit stage to a binary 1 source. This may be accomplished, as illustrated in H6. 6, wherein a simple normally open switch 124 is actuated to apply a binary 1 level signal to a one shot circuit 126. The one shot circuit then applies a momentary binary 1 signal pulse which is inverted by an inverter 128 to apply a binary 0 signal pulse to the shift load input S/L of register 118. As will be appreciated from the following description, during the calculating operation, information bits are shifted from right to left in register 118, as viewed in FIG. 6, until the preset binary 1 bit has been shifted to the left to a position which is identified herein as output stage R This corresponds with the most significant bit stage. When the present binary 1 signal has been shifted to position R,, a reset signal is applied to the reset input of flip-flop I00 to indicate that the ratio calculation has been completed. The output obtained from the ratio shift register 118 at that point in time will correspond with the ratio of the normalized F word to the normalized hypotenuse H This is employed as a modifier for the feed number rate multiplier RMF for purposes of scaling the pulse rate F to a lower pulse rate Fey.

The full adder 112 is a conventional binary adder circuit and effectively provides a subtraction process wherein the value represented by the normalized H word is subtracted from the value in the accumulator for each clock pulse. This is done with binary level signals and to accomplish the subtractive process, an addition process is carried out. The ones complement of the normalized H word is applied to the X input of the full adder. The accumulator contents are applied to the Z input of the adder. A binary l carry in signal is applied to the carry in position by wiring the carry input to a binary l source. The carry output of the full adder is not employed in this operation. The summation output of the adder value of corresponding with A l H This corresponds with the value of A H where A is the value of the binary contents of the accumulator 82. This summation signal is applied as a parallel input to the accumulator and its value is doubled by wiring each bit output to the next higher bit input ofthe accumulator.

Depending upon the results ofa comparison made by comparator 120 of the value of the normalized H word and the value of the accumulator register contents, the output sum of the full adder is doubled and entered into the accumulator, or the contents in the accumulator register is doubled by shifting the contents by one position to the next most significant bit position.

To facilitate an understanding of the manner of operation of the ratio calculation circuitry RC, attention is now directed to FIG. 7 which presents a flow diagram illustrating the operation of the circuitry of FIG. 6. in following the description, it will be useful to refer to both FIGS. 6 and 7 simultaneously. The ratio calculation commences once clock pulses are applied through AND gate 114 and OR gate 116 to the clock input of the ratio shift register 118. The ratio clock signal is also provided as a clock to the accumulator register through AND gate and OR gate 90. The information in the accumulator register is shifted one position to the left to double the value of its contents or the contents will be changed by supplying thereto in parallel format signal corresponding with twice the summation ofthe output of the full adder; that is, 2(A H For each clock pulse, the comparator serves to compare the contents of the A register or accumulator 82 with the value represented by the normalized hypotenuse word H ,obtained from the hypotenuse calculator (FIG. 5). If the value of the contents of the A register is less than that of the normalized hypotenuse H then comparator l20 provides a binary 1 signal on its output. If the comparison indicates that the value of the contents of the A register is equal to or greater than that of the value of the normalized hypotenuse H the comparator provides a binary 0 signal. The binary level of this signal is applied to the shift/load input of the accumulator register 82 to control its mode of operation. When a binary 1 signal is applied to this input, a parallel load operation is instituted whereby a signal corresponding with 2(A H is entered into the accumulator. If a binary 0 signal is applied to this input S/L, then on the next clock pulse applied to the input of accumulator 82, its contents are shifted one place to the left to double its value.

if the first comparison indicates that the value of the contents of the A register is less than that of the normalized hypotenuse H comparator applies abinary 1 signal to cause the accumulator to be parallel loaded and have its contents updated to the value of 2 (A H At the same time the binary l signal from comparator 120 is inverted by an inverter so that a binary 0 signal is shifted into the first bit position of the ratio shift register 118 (the previously preset binary l signal is shifted one position to the left).

When the value of the contents of the accumulator is equal to or greater than the value of the normalized hypotenuse, then the comparator 120 provides a binary 0 signal. This commands the accumulator to double its contents on the next pulse applied to its clock input by shifting the bit pattern therein one position to the left. In addition, the binary 0 signal provided by the comparator 120 is inverted by inverter 130 so that a binary 1 signal is shifted into the first bit position of the ratio shift register 118.

This ratio calculation is continued until the most significant bit position R, of the ratio register "8 is at a binary 1 level. This indicates that the initially preset binary 1 signal at the least significant bit position has been shifted through the register. At this point, the value of the contents in the ratio shift register corresponds with the value of the ratio of the normalized F word to the value of the normalized H word. The operation now stops since a binary 1 signal is applied from the R output of ratio register 118 to reset flip-flop I and thereby prevent further clock pulses from being applied to the registers. This ratio is used as a modifier in scaling down the pulse rate from F to P As will be recalled from the previous description dealing with the scaling circuit SC, the output frequency F is proportional to 2" (F Consequently then, the output frequency F of the feed rate number rate multiplier RMF is proportional to the ratio of the unnormalized F word to the normalized hypotenuse word H This pulse train is applied to the function generator FG which interpolates the pulse train to provide the F command pulses and the F command pulses.

Function Generator (In General) The function generator FG divides the incoming pulse rate F into two output pulse rates which are supplied to the X and Z axes in the proper ratio to produce the programmed slope or radius. As illustrated in FIG. 2, the function generator employs an I rate multiplier IRM and a K rate multiplier KRM. These rate multipliers differ from those employed in the feed rate generator FRG. The rate multipliers in the feed rate generator FRG may be considered as being counter rate multipliers whereas those employed in the function generator FG may be considered as adder rate multipliers.

The input pulse rate to the function generator F0 is the tool velocity rate Fey. The modifier for the I rate multiplier is the number stored in the I counter and is the normalized l word. Similarly, the modifier for the K rate multiplier KRM is the normalized K word. The scaling, however, is further divided by 2. Thus, the X axis pulse rate F equals F I /4). ln circular interpolation, the values of the normalized l word and the normalized K word will change as the control generates an arc. Consequently, the output pulse rates F and P; will not be constant in circular interpolation. For linear operation, the programmed X word is applied to the X displacement control counter XDC as a presettable count and then the counter counts down at the rate of F. to meter the proper number of pulses to the X axis control loop XL. Similarly, the count represented by the 2 word is used to preset the Z displacement control down counter ZDC which then meters the proper number of pulses at the rate of F to the Z axis control loop ZL.

Having now briefly reviewed the overall operation of the function generator, attention is now directed to the circuitry employed.

Function Generator Rate Multiplier Before describing the specific circuitry employed in the function generator illustrated in FIG. 10, attention is first directed to the adder rate multiplier illustrated in FIG. 8 and the accompanying wave forms of FIG. 9. The adder rate multiplier of FIG. 8 is illustrated as a four bit adder rate multiplier. In the description with reference to FIG. 10, the adder rate multiplier is described as a bit adder rate multiplier.

As shown in FIG. 8, the adder rate multiplier includes a four bit binary adder 150 and a four bit accumulator register 152. Such a four bit adder and accumulator are, in themselves, conventional in the art. The four bit output pattern of the accumulator is applied as a four bit input to the adder along with a four bit modifier input M The four bit sum output of the adder is applied as a parallel input to the accumulator register 1S2. Pulses at an input clock rate of F,-,, are applied to the clock input of the accumulator and out pulses at a rate F are obtained from the carry output of the adder. Each time the adder overflows, a carry output is provided as an output frequency pulse. Table ll below illustrates the binary numbers present at the various locations of the four bit adder of HG. 8 with a modifier M of 3 and for a pulse train of 32 input pulses at the input frequency F,,,.

TABLE ll 4 Bit Adder Rate Multiplier With M=3; F,,,,,=F.,, (3H6) Number of Accumulator Modifier Surn Number of F,,, Pulses Output (M) or B A F,,,,, Pulses (E m) (Bl [Al or (2) y l 3 3 6 2 6 3 9 3 9 3 l2 4 l2 3 l5 5 l5 3 2 I 6 2 3 5 7 5 3 8 8 8 3 ll 9 ll 3 l4 ll] [4 3 l 2 ll 1 3 4 l2 4 3 7 l3 7 3 l0 l4 l0 3 l3 l5 l3 3 (l 3 l6 0 3 3 l7 3 3 6 l8 6 3 9 l9 9 3 i2 20 I2 3 l5 21 I5 3 2 4 22 2 3 5 23 5 3 it 24 8 3 ll 25 ll 3 I4 26 I4 3 5 27 l 3 4 28 4 3 7 29 7 3 H) 30 I0 3 l3 3l l3 3 l) 6 32 0 3 3 Examination of the table shows that a multiplier of 3H6 is obtained for this rate multiplier arrangement. Consequently then, three output pulses are obtained for every 16 input pulses or six output pulses are obtained for a pulse train of 32 input pulses. Normalization in the function generator is obtained by selecting a carry output signal depending on the magnitude of the larger of the l or K words. However, there is only one carry output obtained from a conventional four bit integrated circuit adder, such as the four bit adder illustrated in FIG. 8. Carries between bit stages are internal to the typical integrated circuits available and consequently, these carry outputs, if selected, must be generated from the sum outputs. Reference is now made to the wave forms illustrated in FIG. 9. These wave forms are presented for a four bit binary adder and accum ulator as interconnected in FIG. 8 with a modifier having a decimal weight of 3. The sum outputs are employed to generate the carry signals. Specifically, an internal carry exists between sum output 4 and sum output 8 on each change in binary level at sum output 8, as either 

1. A control for use in controlling movement of a machine tool comprising: a source of pulses having a first pulse rate, feed rate generator means including first pulse rate multiplying means having a plurality of states for modifying the pulse rate of pulses derived from said pulse source in accordance with a multiplier having a value M/N, where N is of a fixed value corresponding with the maximum number of states of said multiplying means and M is a first modifying signal having a value depending upon a function of the values of first, second, and third signals, means for receiving a said first, second, and third signal and deriving as said functions thereof the normalized value of each of said signals, and means for developing from said normalized first, second, and third signals a said first modifying signal M; and function generator means including second and third pulse rate multiplying means for each receiving the said modified output pulses from said feed rate generator means and multiplying the pulse rate thereof by a multiplier M''/N'' wherein M'' for said second rate multiplier is a second modifying signal having a value corresponding with said first signal and M'' for said third rate multiplier is a third modifying signal having a value corresponding with said second signal, and wherein N'' is variable having a maximum value of the same amount for each of said second and third rate multiplier means corresponding with the maximum number of states of each of said second and third rate multiplier means, said second and third rate multipliers having means for respectively receiving said first signal and said second signal, and means for effectively normalizing said first and second signals by varying the value of N'' by the same extent in each of said second and third multiplier means in dependence upon the value of the larger of said first and second signals.
 2. A control as set forth in claim 1, wherein said feed rate generator means includes means for developing said first modifying signal such that it has a value corresponding with the ratio of the normalized third signal to the square root of the sum of the squares of the normalized first and second signals.
 3. A control as set forth in claim 2 including means for providing said first and second signals with values respectively corresponding with commanded displacements of said tool along first and second mutually perpendicular axes.
 4. A control as set forth in claim 2 including means for effectively denormalizing said normalized third signal.
 5. A control as set forth in claim 4, wherein said denormalizing means includes fourth pulse rate multiplying means for multiplying said pulses derived from said pulse source by a multiplying factor dependent upon the value of the unnormalized said third signal.
 6. A control as set forth in claim 5, wherein said denormalizing means is interposed between said pulse source and said first pulse rate multiplying means.
 7. A control as set forth in claim 1, wherein said first pulse rate multiplying means is a counter rate multiplier having counting means for counting N-1 pulses derived from said pulse source.
 8. A control as set forth in claim 1, wherein at least one of said first, second and third pulse rate multiplying means is an adder rate multiplier having an adder means and an accumulator means, means for presetting said adder means to a summation corresponding with an associated one of said first, second and third signals, means for applying pulses derived from said pulse source to said accumulator means to cause the contents thereof to be supplied to said adder means to be added to said preset summation.
 9. A control as set forth in claim 8, wherein said first rate Multiplying means is a counter rate multiplier having counting means for counting N-1 pulses derived from said pulse source and said second and third pulse rate multiplying means is each a said adder rate multiplier wherein its said adder means has a maximum summation value of N''-1.
 10. A control as set forth in claim 8, including means for parallel shifting the contents of said accumulator means into said adder means in response to each said applied pulse, said adder means having circuit means for parallel adding said parallel shifted contents to said preset summation contents to provide an updated summation and means for parallel shifting said adder updated summation into said accumulator means.
 11. A control for use in controlling movement of a machine tool comprising a source of pulses having a first pulse rate, feed rate generator means having at least a first rate multiplier means for modifying the pulse rate of pulses derived from said pulse source in dependence upon the value of a first modifying signal to provide feed rate pulses, function generator means having second and third pulse rate multipliers for receiving said feed rate pulses and respectively modifying the pulse rate thereof in dependence upon the value of a second modifying signal and a third modifying signal to respectively provide first command pulses and second command pulses for controlling movement of a said tool, at least one of said rate multipliers comprises: accumulator means having a plurality of stages and having parallel output circuit means for providing a pattern of output signals wherein the pattern of output signals has a value in accordance with the contents of said accumulator means and input circuit means for receiving a pattern of input signals for updating the contents of the accumulator means in accordance with the value of said pattern of input signals, adder means for receiving a modifying pattern of signals corresponding with the associated one of said first, second or third modifying signals and said pattern of output signals from said accumulator means for adding said two patterns of signals in parallel and providing a summation pattern of signals having a value in accordance with the summation of said two patterns of signals; means for iteratively applying said summation pattern signals in parallel to said input circuit means of said accumulator means to update the contents thereof in accordance with the value of said summation pattern of signals at a rate corresponding with the pulse rate of pulses derived from said pulse source, and circuit means connected to said adder means for deriving carry output pulses therefrom whereby said output pulses have a pulse rate in dependence upon the pulse rate of said derived pulses and the value of said received modifying pattern of signals.
 12. A control as set forth in claim 11 wherein said adder means has a plurality of summation output circuits for carrying said pattern of summation signals and a carry output circuit for providing a carry output pulse each time said adder means overflows.
 13. A control as set forth in claim 12 including a plurality of gating means respectively connected to an associated one of said adder summation output circuits, and means for selectively enabling one of said plurality of gating means to pass signals from the selected said summation output circuit to provide said carry output pulses therefrom.
 14. A control as set forth in claim 13 including pulse doubling means for doubling the pulse rate of said signals passed by said enabled gating means.
 15. A control as set forth in claim 11 wherein said circuit means for deriving output pulses from said adder means includes means for varying said pulse rate of said derived pulses by a multiplier of M/N wherein M has a value corresponding with said applied modifying pattern of signals and N has a maximum value corresponding with the maximum number of states of said adder means so thAt the maximum summation of said adder means is N-1.
 16. A control as set forth in claim 15 including means for effectively varying the value of N including means for generating carry pulses for a summation output circuit position of said binary adder means in dependence upon the frequency of signal changes at the next most significant summation output circuit position of said adder means.
 17. A control as set forth in claim 16 including means for doubling the pulse rate of the signal changes at said selected summation position for providing output pulses having a pulse rate in accordance with the carry pulse rate for the next least significant summation position of said adder means.
 18. A control as set forth in claim 17 wherein said at least one of said rate multipliers includes said second and third rate multipliers, means for normalizing said second and third modifying signals comprising: summation output circuit selection means for selecting a corresponding summation output circuit of said adder means in each of said second and third rate multipliers with said selection being dependent upon the larger of said second and third modifying signals.
 19. A control as set forth in claim 18 including: first and second storage means for respectively storing said second and third patterns of modifying signals, and most significant position selection means for detecting the storage position of the most significant signal of the larger of said second and third patterns of modifying signals.
 20. A control as set forth in claim 19, including means for providing a coded signal representative of the said storage position of the most significant signal of the larger of said second and third patterns of modifying signals.
 21. A control as set forth in claim 20, wherein said summation output circuit selection means includes means responsive to said coded signal for selecting said corresponding summation output circuits of said adder means in said second and third rate multipliers. 